IEEE 802.11a 무선 랜 설계 및 검증에 관한 연구
(A) Study on Design and Verification of a IEEE 802.11a Wireless LAN
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IEEE 802.11a 무선랜 설계 검증;
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In this paper, we present an IEEE 802.11a WLAN design method based on a platform, and propose a CODEC processor design method. In order to design IEEE 802.11a WLAN, we used a software-based platform. The IEEE 802.11a baseband processor is designed using hardware description language. we development circuit on interface controller for the data transceive between PHY Layer and MAC Layer. Scrambler and Descrambler to security design source data. Although, we present about implementation of channel coder and Viterbi decoder for Mobile communications & IEEE 802.11a Wireless LAN. In the IEEE 802.11a WLAN decoder provide that Viterbi algorithm and Convolutional encoder by constraint length K=7, (133_(8), 177_(8)) for channel error correction. Interleaver and Deinterleaver designed to exchange serial error by countinuous error in channel error incorporating multipath fading for random error. In order to verification, we provide simulation results This circuit is implemented using Xilinx FPGA device xc2v6000.