Booth 알고리즘을 응용한 고속승산기 구현
(A) Realization of High-Speed Multiplier with Applied Booth Algorithm
BOOTH 고속승산기 전자통신공학;
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In arithmetic units such as microprocessor, multiplication is a process that may delay the entire operation critically. In particular, DSP treatment requires high-speed operation. The purpose of this study is to a new hardware model based on Booth algorithm for multiplication which is a critical source of delayed operation. Multiplier consists of hardwares such as the basic multiplication algorithm, Booth algorithm, Wallace tree algorithm and the arrangement multiplier. When these elements were analyzed in terms of hardware complexity and operation rate, it was found that the arrangement multiplier was the most complicated hardware. In the study, therefore, this researcher attempted to provide ways of designing hardwares for the basic multiplication algorithm, Booth algorithm and Wallace tree, with the arrangement multiplier excluded, and then carried out computer simulations by using Logic Works. To understand Booth algorithm accurately, Chapter Ⅱ of the study described general algorithms of multiplication. Chapter Ⅲ provided a detailed explanation of treatment process using Booth algorithm. Chapter Ⅳ theoretically discussed Wallace Tree and ways of hardware design. Chapter Ⅴ performed simulations through Logic Works program and reviewed and compared those ways of designing as mentioned above.