고성능 디지털시스템을 위한 클럭 분배방식 및 Coplanar와 Microstrip 전송라인의 구조적분석
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a novel clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. It has ideal near zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit and analyze sutiable line structure form comparison by microstrip coming coplanar to FCLs. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than 10ps at 1GHz and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1GHz. Also clock signal regardless of process, voltage, and temperature variation finally this paper verifty that proposed clock distribution scheme superior than conventional clock distribution scheme which used symmetric H-trees.