FPGA Design for Multi-channel, Multi-frequency Electrical Impedance Tomography System using Cascaded Connection
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The design of a fast, flexible and high channel count electrical impedance tomography (EIT) system is important for developing clinical applications. Most research groups have addressed this using a re-configurable integrated circuit such as a digital signal processor (DSP) or a field programmable gate array (FPGA) because of their flexibility, high speed and computing power. FPGAs have advantages for high speed, distributed and parallel processing with increased flexibility. One of the main advantages of EIT over other imaging methods is its comparatively high temporal resolution which is attractive for simultaneous measurements with other biosignal measurement modalities such as electrocardiography (ECG), electroencephalography (EEG) and respiration monitoring to perform complementary and comparative physiological studies. However there is a lack of EIT systems with the capability of interfacing with other biosignal measurement modalities. Most EIT systems are time multiplexed single channel systems with limits on the number of channels, measurement performance and functionality, such as multi-frequency operation. To address this issue we developed a fully parallel, multi-channel KHU Mark2.5 EIT system based on FPGAs. In order to improve spatial resolution and maintain the high temporal resolution we took advantage of various FPGA aspects to develop a KHU Mark2.5 EIT system. This is based on one intra-network controller FPGA and a number of impedance measurement module (IMM) FPGAs. The intra-network controller arbitrates commands and data between the main controller and all the IMMs through multiple serial ports. The EIT system includes a flexible interface to operate with other medical devices, either receiving a trigger signal or transmitting a timing signal for synchronizing operation. This is achieved with a scan start timing and control module which generates the scan start signal and broadcasts it to all the IMMs. All IMMs receive the scan start command and generate the waveform, acquire, demodulate and send data to the personal computer (PC) in a pipelined mode while operating in parallel. This work describes the FPGA based intra-network controller and IMM controller with associated algorithms. Simulations of the operating modes, phantom measurements of multiplexing modes and in-vivo ECG-gated imaging tests were carried out to demonstrate and validate the design. To improve the spatial resolutions while maintaining the flexibility and portability of the system, we implemented clock synchronization algorithm based on IEEE 1588 precision time protocol standard, into the intra-network controller. Resistor phantom studies are carried out successfully by using two KHU Mark 2.5 EIT systems in cascaded connection. Simulations of single and mixed frequency generation and system timing were successful and confirm the operation of all modes. High speed performance with maximum of 100 frames/s and a unique multiplexing operation was demonstrated. Successful images were obtained with multi-frequency waveform multiplexing and frequency-division multiplexing, parallel processing, selfcalibration and ECG-gated imaging operation. The parallel architecture in simultaneous multi-frequency imaging improved the speed by about more than three times. An FPGA based EIT system which features a pipelined structure and expandable measurement channels was designed and implemented on FPGAs. The design and implementation of FPGA functions is described and simulated in detail. All modes were demonstrated in phantom experiments and biosignalgating was demonstrated with an in-vivo ECG-gated imaging test in a dog experiment. Currently the speed improvement offered by the parallel design with multi-frequency imaging is limited by the resources of the FPGA (EP3C10F256 Altera, USA). These may be alleviated in future designs.