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Optimized Implementation of Hamming Decoder for Software Defined Radio using Graphics Processing Units 원문보기

  • 저자

    이슬람 엠디 소히둘

  • 학위수여기관

    울산대학교

  • 학위구분

    국내석사

  • 학과

    컴퓨터공학전공

  • 지도교수

    Jongmyon Kim

  • 발행년도

    2014

  • 총페이지

  • 키워드

  • 언어

    eng

  • 원문 URL

    http://www.riss.kr/link?id=T13540273&outLink=K  

  • 초록

    Hamming code is a linear-block code, widely employed as a forward error correction (FEC) technique in the area of wired and wireless networks for reliable data communication. Many existing wireless communication systems employed application specific integrated circuits (ASICs) based dedicated Hamming decoders for particular communication protocol standards including worldwide interoperability for microwave access (WiMAX, IEEE 802.16), Wi-Fi (IEEE802.11), wideband code division multiple access (W-CDMA), global system for mobile communication (GSM), digital video broadcasting-satellite second generation (DVB-S2), and digital high definition TV. However, the fixed functionality of such ASIC devices limits to support emerging communication standards because they were fixed for their own coding scheme, data rate, frequency range, and types of modulation. In addition, manufacturing cost and time-to-market of hardware devices are very high to keep up with rapidly changing technology. Software defined radio (SDR) is an emerging technology offering software alternatives of the existing hardware solutions for wireless communication and the SDR technology has recently drawn wide attention to the communication research community. It allows system reconfiguration by using software commands because users are required to switch from one standard to another standard very frequently in recent circumstances. In addition, it enables the radio device to change transmitting and receiving characteristics by software means without altering the hardware platform. In SDR, some or all of the physical layer functions are written in software, which runs on general-purpose programmable processors (GPPs) and digital signal processors (DSPs). GPPs or DSPs offer the necessary programmability and flexibility for various SDR applications. However, neither GPPs nor DSPs will be able to meet the much higher levels of performance required by the high computational workloads in SDR. Among the many available computational models, graphics processing units (GPUs) perform better with latency-tolerant, highly parallel and independent tasks. Attracted by the features of modern GPUs, communication research community is focussing on hgihly scalabale, flexible, and programmable decoder on GPU for SDR-based communication systems. The standard Hamming code can guarantee single-bit error correction but single-bit error correction is enough in real-world applications. However, Extended Hamming code can efficiently support both single- and multiple-bit error protections. The contribution of this thesis consists of three folds- (i) GPU implementation of standard or fundamental Hamming decoder for single-bit error protection, (ii) GPU implementation of extended Hamming decoder for single bit as well as multiple bit error protection, and (iii) practical application of the GPU based decoder in E-Health system for secure transmission of watermarked medical images. Efficient decoder design is attempted from a number of GPU computing viewpoints. The special implementation issues include (a) proper mapping to achieve massive parallelism, (b) asynchronous memory transfer between the CPU and GPU to reduce memory transfer latency, (c) coalesced memory access ensuring faster read and write in the GPU, (d) more use of on-chip shared memory, as opposed to off-chip global memory, since overhead of data transaction to access global memory is comparatively higher than that of shared memory. These features are adopted for a significant reduction in execution time and energy consumption. The performance of the proposed GPU based decoder is compared with that of CPU and DSP in terms of execution time, speedup, and energy efficiency. Experimental results demonstrate that the GPU-based decoder yields a tremendous increase in speed over the sequential approaches. We validated our proposed approach using a Compute Unified Device Architecture (CUDA) enabled NVIDIA GeForce GTX 560 graphics card.


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