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시간 제약 조건 하에서 저전력을 고려한 CLB구조의 CPLD 기술 매핑 알고리즘
CLB-Based CPLD Technology Mapping Algorithm for Power Minimization under Time Constraint

김재진   (극동정보대학 전산정보처리과  ); 김희석   (청주대학교 정보통신공학부UU0001267  );
  • 초록

    In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.


  • 참고문헌 (14)

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 저자의 다른 논문

  • 김희석 (32)

    1. 1985 "Yield 최대화를 고려한 회로설계" 電子工學會誌 = Journal of the Korean Institute of Electronics Engineers 22 (5): 102~109    
    2. 1989 "상태합성기 설계를 위한 상태 CHDL 기술 및 기호최소화 알고리듬개발" 전자공학회논문지 = Journal of the Korean Institute of Telematics and Electronics 26 (5): 127~136    
    3. 1994 "PLD 설계용 툴 개발에 관한 연구" 정보처리논문지 = The transactions of the Korea Information Processing Society 1 (3): 391~397    
    4. 1995 "Device fitting이 고려된 PLD 설계용 Tool 개발" 電子工學會論文誌. Jounnal of the Korea institute of telematics and electronics. A. A a32 (10): 102~110    
    5. 1998 "EDIF Netlist를 이용한 PLD 설계용 툴 개발" 정보처리논문지 = The transactions of the Korea Information Processing Society 5 (4): 1025~1032    
    6. 1999 "시간적 조건에서 실행시간을 개선한 CPLD 기술 매핑 알고리즘 개발" 한국OA학회논문지 = Journal of The Korean Institute of Office Automation 4 (3): 35~46    
    7. 1999 "시간제약 조건하에서 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발" 한국OA학회논문지 = Journal of The Korean Institute of Office Automation 4 (4): 15~24    
    8. 1999 "시간제약 조건을 고려한 CPLD 기술 매핑 알고리즘 개발" 電子工學會論文誌. Journal of the Korean Institute of Telematics and Electronics. C c36 (6): 9~17    
    9. 2000 "ASIC설계를 위한 하드웨어 할당 및 바인딩 알고리듬" 정보처리논문지 = The transactions of the Korea Information Processing Society 7 (4): 1255~1262    
    10. 2000 "시간제약 조건하에서 순차 회로를 위한 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발" 電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체 37 (4): 80~89    

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