본문 바로가기
HOME> 논문 > 논문 검색상세

논문 상세정보

ETRI journal v.26 no.6, 2004년, pp.575 - 582  
본 등재정보는 저널의 등재정보를 참고하여 보여주는 베타서비스로 정확한 논문의 등재여부는 등재기관에 확인하시기 바랍니다.

A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications

Park, Chang-Hyun    (System LSI Division, Samsung Electronics   ); Oh, Myung-Hwan    (System LSI Division, Samsung Electronics   ); Kang, Hee-Sung    (System LSI Division, Samsung Electronics   ); Kang, Ho-Kyu    (System LSI Division, Samsung Electronics  );
  • 초록

    Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.


  • 주제어

    Fully-depleted SOI .   Si selective epitaxial growth .   double raised .   single raised .   series resistance .   self-heating .   static noise margin.  

  • 참고문헌 (12)

    1. Static-Noise Margin Analysis of MOS SRAM Cells , Seevinck, E.;List, F.J.;Lohstroh, J. , IEEE J. Solid-State Circuits / v.22,pp.748,
    2. Fully Depleted SOI CMOS Device with Raised Source/Drain for 90 nm Embedded SRAM Technology , Oh, M.H.;Park, C.H.;Kang, H.S.;Oh, C.B.;Kim, Y.W.;Suh, K.P. , Solid State Devices and Materials / v.,pp.756,
    3. A Novel Structure MOSFET's Fabricated by Using SiGe Selective Epitaxial Growth Method and Laser Induced Atomic Layer Doping Method , Lee, Yong-Jae;Choi, Young-Shig;Bea, Ji-Chel , J. Korean Phys. Soc. / v.41,pp.82,
    4. Fabrication of a $0.2-{\mu}m$ Ultra-Thin SOI Inverted Sidewall Recessed Channel CMOS with Single-Type Polysilicon Gate , Woo, Dong-Soo;Park, Boo-Sik;Lee, Jong-Duk;Park, Byung-Gook , J. Korean Phys. Soc. / v.40,pp.68,
    5. Robust Process Integration of $0.78m^2$ Embedded SRAM with NiSi Gate and Low-K Cu Interconnect for 90 nm SoC Applications , Kim, Y.W.;Ahn, J.H.;Park, T.S.;Oh, C.B.;Lee, K.T.;Kang, H.S.;Lee, D.H.;Ko, Y.G.;Cheong, K.S.;Jun, J.W.;Liu, S.H.;Kim, J.;Nam, J.L.;Ha, S.R.;Park, J.B.;Song, S.A.;Suh, K.P. , VLSI Tech. Dig. / v.,pp.69,
    6. Thermal Agglomeration of Thin Single Crystal Si on $SiO_2$ in Vacuum , Ono, Y.;Nagase, M.;Tabe, M.;Takahashi, Y. , Jpn. J. Appl. Phys. / v.34,pp.1728,
    7. Characteristics of SOI FET's Under Pulsed Conditions , Jenkins, K.A.;Sun, J.Y.C.;Gautier, J. , IEEE Trans. Electron Devices / v.44,pp.1923,
    8. Effects of Shallow Trench Isolation on Silicon-on-Insulator Devices for Mixed Signal Processing , Lee, Hyeok-Jae;Park, Young-June;Min, Hong-Shick;Lee, Jong-Ho;Shin, Hyung-Soon;Sun, Woo-Kyung;Kang, Dae-Gwan , J. Korean Phys. Soc. / v.40,pp.653,
    9. Experimental $0.25-{\mu}m-Gate$ Fully Depleted CMOS/SIMOX Process Using a New Two-Step LOCOS Isolation Technique , Ohno, T.;Kado, Y.;Harada, M.;Tsuchiya, T.T. , IEEE Trans. Electron Devices / v.42,pp.1481,
    10. Modeling the I-V Characteristics of Fully Depleted Submicrometer SOI MOSFET’s , Hsiao, T.C.;Kistler, N.A.;Woo, J.C.S. , Electron Device Lett. / v.15,pp.45,
    11. A 50 nm Depleted-Substrate CMOS Transistor (DST) , Chau, R.;Kavalieros, J.;Doyle, B.;Murthy, A.;Paulsen, N.;Lionberger, D.;Barlage, D.;Arghavani, R.;Roberds, B.;Doczy, M. , Int. Electron Device Meet. Technical Digest / v.,pp.62,
    12. Comprehensive Study on AC Characteristics in SOI MOSFETs for Analog Applications , Tseng, Y.C.;Huang, W.M.;Monk, D.;Diaz, D.;Ford, J.M.;Woo, J.C.S. , Symp. VLSI Tech. Dig. / v.,pp.112,

 활용도 분석

  • 상세보기

    amChart 영역
  • 원문보기

    amChart 영역

원문보기

무료다운로드
유료다운로드
  • 원문이 없습니다.

유료 다운로드의 경우 해당 사이트의 정책에 따라 신규 회원가입, 로그인, 유료 구매 등이 필요할 수 있습니다. 해당 사이트에서 발생하는 귀하의 모든 정보활동은 NDSL의 서비스 정책과 무관합니다.

원문복사신청을 하시면, 일부 해외 인쇄학술지의 경우 외국학술지지원센터(FRIC)에서
무료 원문복사 서비스를 제공합니다.

NDSL에서는 해당 원문을 복사서비스하고 있습니다. 위의 원문복사신청 또는 장바구니 담기를 통하여 원문복사서비스 이용이 가능합니다.

이 논문과 함께 이용한 콘텐츠
이 논문과 함께 출판된 논문 + 더보기