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ETRI journal v.26 no.6, 2004년, pp.545 - 554  
본 등재정보는 저널의 등재정보를 참고하여 보여주는 베타서비스로 정확한 논문의 등재여부는 등재기관에 확인하시기 바랍니다.

An Area Optimization Method for Digital Filter Design

Yoon, Sang-Hun   (Department of Electronic Engineering, Hanyang UniversityUU0001519  ); Chong, Jong-Wha   (Department of Electronic Engineering, Hanyang UniversityUU0001519  ); Lin, Chi-Ho   (Department of Computer Science, Semyung UniversityUU0000787  );
  • 초록

    In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.


  • 주제어

    Digital filter .   flattened coefficient .   adder sharing .   architecture.  

  • 참고문헌 (9)

    1. Designing Multiplier Blocks with Low Logic Depth , Dempster, A.;Demirsoy, S.;Kale, I. , Proc. IEEE Int’l Symp. Circuits and Systems / v.,pp.V-773-V-776,
    2. Subexpression Sharing in Filters Using Canonical Signed Digit Multipliers , Hartley, R. , IEEE Trans. Circuits Syst. II / v.43,pp.677-688,
    3. Design of High-Speed Multiplierless Filters Using a Nonrecursive Signed Common Subexpression Algorithm , Martinez-Peiro, M.;Boemo, E.I.;Wanhammar, L. , IEEE Trans. Circuits Syst. II / v.49,pp.196-203,
    4. FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders , Kang, H.J.;Park, I.C. , IEEE Trans. Circuits Syst. II / v.48,pp.770-777,
    5. Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters , Dempster, A.;Macleod, M.D. , IEEE Trans. Circuits Syst. II / v.42,pp.569-577,
    6. Primitive Operator Digital Filter , Bull, D.R.;Horrocks, D.H. , Proc. Inst. Ele. Eng. Circuits, Devices and Systems / v.138,pp.401-412,
    7. Optimization of Canonical Signed Digit Multipliers for Filter Design , Hartley, R. , Proc. IEEE Int’l. Symp. Circuits Systems / v.,pp.1992-1995,
    8. Multiple Constant Multiplication: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination , Potkonjak, M.(et al.) , IEEE Trans. Computer-Aided Design / v.15,pp.151-165,
    9. FIR Digital Filter Implementation Using Flattened Coefficient , Yoon, S.H.;Chong, J.W. , Proc. IEEE Int’l Symp. Circuits and Systems / v.,pp.III-363-III-366,

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  • Yoon, Sang-Hun (2)

    1. 2007 "새로운 DBO-CSS 수신기 구조" 電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. TC, 통신 44 (4): 59~64    
  • Chong, Jongwha (86)

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