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ETRI journal v.26 no.6, 2004년, pp.520 - 534  
본 등재정보는 저널의 등재정보를 참고하여 보여주는 베타서비스로 정확한 논문의 등재여부는 등재기관에 확인하시기 바랍니다.

An Efficient Built-in Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories

Kang, Dong-Chual    (School of Electrical Engineering, University of Ulsan   ); Park, Sung-Min    (Department of Information Electronics Engineering, Ewha Womans University   ); Cho, Sang-Bock    (School of Electrical Engineering, University of Ulsan  );
  • 초록

    As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.


  • 주제어

    Memory .   BIST .   NBLSF .   NPSF .   testing.  

  • 참고문헌 (11)

    1. Implementation of a Built-in Self Test Circuit for High Density Memory Test Using a New Tiling Method , Kang, D.C.;Cho, S.B. , Proc. ITC-CSCC'98 / v.,pp.1781-1784,
    2. A New Test Algorithm for Bit-Line Sensitive Faults in Super High-Density Memories , Kang, D.C.;Lee, J.H.;Cho, S.B. , Proc. IEEE The Fifth Russian-Korean Int’l Sym. on Science and Technology / v.1,pp.198-201,
    3. DRAM Design , Yoo, H.J. , / v.,pp.13-71,
    4. Open Defects in CMOS RAM Address Decoders , Sachdev, M. , IEEE Design & Test of Computers / v.14,pp.26-33,
    5. Testing Memories for Single-Cell Pattern-Sensitive Faults , Hayes, J.P. , IEEE Trans. Comput. / v.29,pp.,
    6. Detection of Pattern-Sensitive Faults in RAMs , Hayes, J.P. , IEEE Trans. Comput. / v.24,pp.150-157,
    7. Semiconductor Memories , Sharma, A.K. , / v.,pp.151-154,
    8. Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories , Suk, D.S.;Reddy, S.M. , IEEE Trans. Comput. / v.29,pp.419-429,
    9. Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories , Mazumder, P.;Patel, J.H. , IEEE Trans. Comput. / v.38,pp.394-407,
    10. An Algorithm to Test RAMs for Physical Neighborhood Sensitive Faults , Franklin, M.;Saluja, K.K. , Proc. IEEE ITC 1991 / v.,pp.675-684,
    11. An Integrated Test Concept for Switched-Capacitor Dynamic MOS RAM's , Lo, T.C.;Guidry, M.R. , IEEE J. Solid-State Circuits / v.12,pp.693-703,

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