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Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

Choi, Byung-Kil   (Dept. of Electronic and Electrical Engineering, Kyungpook National UniversityUU0000096  ); Park, Ki-Heung   (Dept. of Electronic and Electrical Engineering, Kyungpook National UniversityUU0000096  ); Han, Kyoung-Rok   (Dept. of Electronic and Electrical Engineering, Kyungpook National UniversityUU0000096  ); Kim, Young-Min   (Dept. of Electronic and Electrical Engineering, Kyungpook National UniversityUU0000096  ); Lee, Jong-Ho   (Dept. of Electronic and Electrical Engineering, Kyungpook National UniversityUU0000096  );
  • 초록

    Threshold voltage ( $V_{th}$ ) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ( $x_h$ ) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.


  • 주제어

    Barrier lowering .   Bulk FinFET .   double-gate .   modeling .   threshold voltage.  

  • 참고문헌 (10)

    1. Byung-Kil Choi, Kyoung-Rok Han, Young Min Kim, Young June Park, and Jong-Ho Lee, 'Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs),' in IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 537-545, Mar. 2007 
    2. Gulzar A. Kathawala, Brain Winstead and Umberto Ravaidi, 'Monte Carlo simulation of double-gate MOSFETs,' IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2467-2473, Dec. 2003 
    3. Tai-Su Park, Hye Jin Cho, Jeong Dong Choe, Sang Yeon Han, Donggun Park, Kinam Kim, Euijoon Yoon, and Jong-Ho Lee, 'Characteristics of the Full CMOS SRAM Cell Using Body-Tied TG MOSFETs (Bulk FinFETs),' IEEE Trans. Electron Devices, vol. 53, no. 3, pp. 481-487, Mar. 2006 
    4. SILVACO International, ATLAS User's Manual, 2007. [Online]. Available: http://www.silvaco.com 
    5. International Technology Roadmap for Semiconductors, 2007. [Online]. Available: http://public.itrs.net 
    6. Byung-Kil Choi, Young Min Kim, Kyoung-Rok Han, Young June Park, and Jong-Ho Lee, 'Threshold Voltage Modeling of Bulk FinFETs by Considering Corner Effect,' in Si Nanoelectronics Tech. Dig., 2006, pp. 67-68 
    7. T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, 'Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers,' in Symp. on VLSI Tech. Dig., 2003, pp. 135-136 
    8. Tai-su Park, Euijoon Yoon, Jong-Ho Lee, 'A 40nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer,' Physica E, vol. 19, no. 1, pp. 6-12, 2003 
    9. T. Park, H. J. Choe, S. Y. Han, S.-M. Jung, B. Y. Nam, O. I. Kwon, J. N. Han, H. S. Kang, M. C. Chae, G. S. Yeo, S. W. Lee, D. Y. Lee, D. Park, K. Kim, E. Yoon, and J. H. Lee, 'Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs),' in IEDM Tech. Dig., Dec. 2003, pp. 27-30 
    10. Qiang Chen, Evans M. Harrel and James D. Meindl, 'A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs,' IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003 

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