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Journal of semiconductor technology and science v.7 no.2, 2007년, pp.120 - 131   피인용횟수: 2

Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

Gupta, Ritesh   (Department of Electronic Science, University of Delhi South Campus  ); Aggarwal, Sandeep Kumar   (Department of Electronic Science, University of Delhi South Campus  ); Gupta, Mridula   (Department of Electronic Science, University of Delhi South Campus  ); Gupta, R.S.   (Department of Electronic Science, University of Delhi South Campus  );
  • 초록

    A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.


  • 주제어

    Gate-insulator geometries .   field plate .   gate-stack .   retrograde doping .   metal workfunction .   cut-off frequency .   breakdown voltage .   hot-carrier effect .   Field engineering .   DIBL .   threshold voltage.  

  • 참고문헌 (51)

    1. Bhavna agarwal et al, 'Device Parameter Optimization for reduced short channel effects in retrograde doping MOSFET's', IEEE Trans Electron Devices, vol. 43. no. 2, pp. 363-368, 1996 
    2. S. C. Williams et al, 'Scaling Trends for device performance and reliability in channel-engineered n-MOSFET's', IEEE Trans Electron Devices, vol. 45, no. 1, pp. 254-260, 1998 
    3. Indranil de et al, 'Impact of super-steepretrograde channel doping profiles on the performance of scaled devices', IEEE Trans Electron Devices, vol. 46, no. 8, pp. 1711-1717, 1999 
    4. M. Jagadesh kumar et al, 'Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs', IEEE Trans Electron Devices, vol. 51, no. 4, pp. 569-574, 2004 
    5. N. Q. Zhang et al, 'High breakdown GaN HEMT with overlapping gate structure', IEEE Electron Device Letters, vol. 21, no. 9, pp. 421-423, 2000 
    6. Horng-chih Lin et al, 'A novel thin film transistor with self aligned field induced drain', IEEE Trans Electron device Letters, vol. 22, no. 1, pp. 26-28, 2001 
    7. Shreepad Karmalkar et al, 'Enhancement of breakdown voltage in AlGaN/GaN High electron mobility transistors using a field plate', IEEE Trans Electron Device, vol.48, no.8, pp. 1515-1521, August 2001 
    8. Huili Xing et al, 'High breakdown voltage AlGaN-GaN HEMTs achieved by multiple field plate', IEEE Electron Device Letters, vol. 25, no. 6, pp. 161-163, 2004 
    9. Guangjun Cao et al, 'Comparative study of drift region designs in RF LDMOSFETs', IEEE Trans Electron Devices, vol. 51, no. 8, pp. 1296-1303, 2004 
    10. Shreepad Karmalkar et al, 'Field Plate Engineering for HFETs', IEEE Trans Electron Device, vol.52, no.12, pp. 2534-2540, December 2005 
    11. K. Elgaid, H. McLelland, M. Holland, D. A. J. Moran, C. R. Stanley, and I. G. Thayne, '50-nm T-Gate Metamorphic GaAs HEMTs With fT of 440 GHz and Noise Figure of 0.7 dB at 26 GHz', IEEE Electron Device Letters, Vol. 26, no. 11, p. 784, November 2005 
    12. Ronald Grundbacher et al, 'Utilization of an Electron Beam Resist Process to Examine the Effects of Asymmetric Gate Recess on the Device Characteristics of AlGaAs/InGaAs PHEMT's', IEEE Trans Electron Device, Vol. 44, no. 12, p. 2136, December 1997 
    13. M. Chertouk et al, 'Metamorphic InAlAs-InGaAs HEMT' s on GaAs Substrates with a Novel Composite Channels Design', IEEE Electron Device Letters, Vol. 17, no. 6, p. 213, June 1996 
    14. P. M Smith, S. M. J. Jiu, M. Y. Kao, P. Ho, S. C. Wang, K. H. G. Duh, S.T. Fu. And P. C. Chao, 'W-band high efficiency InP-based power HEMT with 600 GHz f/sub max/...,' IEEE Microwave and Guided Wave Lett., Vol. 5, p. 230, 1995 
    15. S. K. Chung et al, 'An Analytical Method for two-dimensional field distribution of MOS structure with a finite field plate', IEEE Trans Electron Devices, vol. 42, no. 1, pp. 192-194, 1995 
    16. Hyungsoon shin et al, 'MOSFET drain engineering analysis for deep-submicrometer dimensions: a new structural approach', IEEE Trans Electron Devices, vol. 39, no. 8, pp. 1922-1927, 1992 
    17. Romain Gwoziecki et al, 'Optimization of Vth roll-off in MOSFET's with advanced channel architecture-retrograde doping and pockets', IEEE Trans Electron Devices, vol. 46, no. 7, pp. 1551-1561, 1999 
    18. C. S. Whelan et al, 'Low Noise $In_{0.32}(AlGa)_{0.68}As/In_{0.43}Ga_{0.57}As$ Metamorphic HEMT on GaAs Substrate with 850 mW/mm Output Power Density', IEEE Electron Device Letters, Vol. 21, no. 1, p. 5, January 2000 
    19. A. Lepore, M. Levy, H. Lee, and E. Kohn, 'Fabrication and Performance of 0.1-pm Gate-Length AlGaAs/GaAs HEMT's with Unity Current Gain Cutoff Frequency in Excess of 110 GHz', IEEE Trans Electron Device, Vol. 35, no. 12, p. 2441, December 1988 
    20. Ritesh Gupta et al, 'A New simplified Analytical Short-channel Threshold Voltage Model for InAlAs/InGaAs Heterostructure InP based Pulsed Doped HEMT', Solid State Electronics Vol. 48, no.3, pp. 437-443, 2004 
    21. Woo-Hyeong Lee et al, 'Gate Recessed (GR) MOSFET with selectively Halo-doped channel and deep graded source/drain for deep submicron CMOS', IEDM 93, pp. 135-138, 1993 
    22. K.L. Tan et al, '94-GHz $0.1{\mu}m T-gate low-noise pseudomorphic InGaAs HEMT's' IEEE Electron Device Letters, Vol. 11, no. 12, December 1990 
    23. Kartikeya mayaram et al, 'A model for the electric field in Lightly doped drain structures', IEEE Trans Electron Devices, vol. 34, n0.7, pp. 1509-1518, 1987 
    24. C. Basavana Goud et al, 'Analysis and optimal design of semi-insulator passivated high voltage field plate structures and comparison with dielectric passivated structures', IEEE Trans Electron Devices, vol. 41, no. 10, pp. 1856-1865, 1994 
    25. K. P. Brieger et al, 'The contour of an optimal field plate-an analytical approach', IEEE Trans Electron Devices, vol. 35, no. 5, pp. 684-688, 1988 
    26. Meng Tao, Feng Gao, and Changyuan Chen, 'Misalignment Tolerance in the 100-nm T-Gate Recessed-Channel Si nMOSFET', IEEE Trans. Electron Device, Vol. 48, no. 12, p. 2951, December 2001 
    27. Jackson JD, Classical Electrodynamics, New York Wiley 1975 
    28. Ming-Jyh Hwu, Hsien-Chin Chiu, Shih-Cheng Yang, and Yi-Jen Chan, 'A Novel Double- Recessed 0.2-_m T-Gate Process for Heterostructure InGaP-InGaAs Doped-Channel FET Fabrication', IEEE Electron Device Letters, Vol. 24, no. 6, p. 381, June 2003 
    29. T. Enoki, E. Sano, and T. Ishibashi, 'Prospects of InP Based IC Technologies for 100 Gbit/s - Class lightwave communications systems,' International Journal of High Speed Electronics and Systems, Vol. 11, Pp. 137-158, 2001 
    30. Ching-Yeu Wei et al, 'A novel CID structure for improved breakdown voltage', IEEE Trans Electron Devices, vol. 37, no. 3, pp. 611-617, 1990 
    31. Y. Ando et al, '12 W/mm recessed gate AlGaN/GaN heterojunction Field Plate FET', IEDM, pp. 563-566, 2003 
    32. Shreepad Karmalkar et al, 'Very high voltage AlGaN-GaN high electron mobility transistors using a field plate deposited on a stepped insulator', Solid State Electron., vo.45, pp. 1645-1652, Sept.2001 
    33. K.W. Terrill, 'An Analytical model for the channel electric field in MOSFET's with gradeddrain structures', IEEE Electron Device Letters, vol. 5, no.11, pp. 440-442, 1984 
    34. K. Kurimoto et al, 'A T-gate Overlapped LDD device with high circuit performance and high reliability', IEDM, pp. 541-544, 1991 
    35. Y. C. Lien et al, 'Low-Noise Metamorphic HEMTs with Reflowed 0.1-${\mu}m$ T-Gate', IEEE Electron Device Letters, Vol. 25, no. 6, p. 348, June 2004 
    36. Ronald Grundbacher et al, 'Utilization of an electron beam resist process to examine the effects of asymmetric gate recess on the device characteristics of AlGaAs/InGaAs pHEMT's', IEEE Trans Electron Device, Vol. 44, no. 12, pp. 2136-2142, December 1997 
    37. Takashi Hori et al, 'Deep-submicrometer largeangle tilt implanted drain (LATID) technology', IEEE Trans Electron Devices, vol. 39, no. 10, pp. 2312-2324, 1992 
    38. K.G.Pani et al, 'Modeling of high current density trench gate MOSFET', IEEE Trans Electron Devices, vol. 47, no. 12, pp. 2420-2428, 2000 
    39. D. S. Wen et al, 'A Self Aligned Inverse-T gate fully overlapped LDD Device for Sub-Half Micron CMOS', IEDM, pp. 765-768, 1989 
    40. D. Geiger et al, 'InGaP/InGaAs HFET with High Current Density and High Cut-Off Frequencies', IEEE Electron Device Letters, Vol. 16, no. 6, p. 259, June 1995 
    41. Ritesh Gupta et al, 'Analytical Model for Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) for its High Frequency and High Power Applications', Journal of Semiconductor Science and Technology, Vol.6, no.3, pp. 189-198, 2006     
    42. Tohru Mogami et al, 'Hot carrier effects in Surface-channel PMOSFETs with $BF_{2-}$ or boron implanted gates', IEDM, pp. 533-536, 1991 
    43. James E. Chung et al, 'Performance and Reliability design issues for deep-submicrometer MOSFET's', IEEE Trans Electron Devices, vol. 38, no. 6, pp. 545-554, 1991 
    44. Le-Tien Jung et al, 'Simulation, fabrication and characterization of a novel P-I-N-drain MOSFET structure for hot carrier suppression', IEEE Trans Electron Devices, vol. 42, no. 9, pp. 1591-1599. 1995 
    45. M-L Chen et al, 'Self-Aligned Silicided Inverse-T gate LDD devices for sub-half micron CMOS technology', IEDM, pp. 829-832, 1990 
    46. A. I. Akinwande et al, 'A self Aligned gate Lightly doped drain (Al,Ga)As/GaAs MODFET', IEEE Electron Device Letters, vol. 9, no.6, pp. 275-277, 1988 
    47. Shreepad Karmalkar et al, 'Resurf AlGaN/GaN HEMT for high voltage power switching', IEEE Electron Device Letters, vol. 22, no.8, pp. 373-375, August 2001 
    48. Tomohisa Mizuno et al, '$Si_{3}N_{4}/SiO_{2}$ spacer Induced High reliability in LDDMOSFET and its simple degradation model', IEDM, pp. 234- 237, 1988 
    49. K. Asano et al, 'Novel high power AlGaAs/GaAs HFET with a field modulating plate operated at 35 V drain voltage', IEDM, pp. 59-62, 1998 
    50. Ritesh Gupta et al, 'An Analytical Non-Linear Charge Control Parasitic Resistance Depending Model for InAlAs/InGaAs/InP HEMT Characteristics', Microelectronics Engineering, Vol. 60, no. 3 - 4, pp. 323-337, 2002 
    51. Ritesh Gupta et al, 'An Analytical Model for Discretized Doped InAlAs/InGaAs heterojunction HEMT for Higher Cut-Off Frequency and Reliability', Microelectronics Journal, Vol. 37/9 pp. 919-929 2006 
  • 이 논문을 인용한 문헌 (2)

    1. 2008. "" Journal of semiconductor technology and science, 8(2): 115~120     
    2. 2010. "" Journal of semiconductor technology and science, 10(1): 66~77     

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