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Journal of semiconductor technology and science v.7 no.3, 2007년, pp.209 - 213   피인용횟수: 1

Compact Gate Capacitance Model with Polysilicon Depletion Effect for MOS Device

Abebe, H.   (University of Southern Califormia Information Science Institute, MOSIS service  ); Morris, H.   (San Jose State UniversityUU0014167  ); Cumberbatch, E.   (Claremont Graduate University  ); Tyree, V.   (University of Southern Califormia Information Science Institute, MOSIS service  );
  • 초록

    The MOS gate capacitance model presented here is determined by directly solving the coupled Poisson equations on the poly and silicon sides, and includes the polysilicon (poly) gate depletion effect. Our compact gate capacitance model exhibits an excellent fit with measured data and parameter values extracted from data are physically acceptable. The data are collected from 0.5, 0.35, 0.25 and $0.18{\mu}m$ CMOS technologies.


  • 주제어

    Device modeling .   gate capacitance .   MOSFETs .   polysilicon depletion effect.  

  • 참고문헌 (11)

    1. R. Rios, N. D. Arora and C. L. Huang, 'An Analytic polysilicon depletion effect model for MOSFET's, ' IEEE Electron Device Letters, Vol. 15, No. 4, April (1994) 
    2. A. Ortiz-Conde, F. J. Garcia Sanchez, M.Guzman, 'Exact Analytical Solution of Channel Surface Potential as an Explicit Function of Gate Voltage in Undoped-body MOSFETs Using the Lambert W function and a Threshold Voltage Definition,' Solid-State Electronics 47 pp. 2067-2074 (2003) 
    3. H. Abebe, E. Cumberbatch, H. Morris and V. Tyree, 'Numerical and analytical results of the polysilicon gate depletion effect on MOS gate capacitance,' IEEE UGIM Proceedings, pp. 111-115, June 25-28, (2006), San Jose, CA 
    4. S. Lo, D. Buchanan, and Y. Taur, 'Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides.' IBM J. Res. Develop. Vol. 43, No. 3, May (1999) 
    5. A. Gupta et al., 'Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices,' IEEE Electron Device Letters, Vol. 18, No. 12, December (1997) 
    6. R. F. Pierret, Field Effect Devices, Addison-Wesley, second edition, Vol. IV, (1990) 
    7. T. L. Chen and G. Gildenblat, 'Analytical approximation for the MOSFET surface potential,' Solid State Electronics, 45, pp.335-339, (2001) 
    8. C.-H, Choi et al.., 'Gate length dependent polysilicon depletion effects,' IEEE Electron Device Letters, Vol. 23, No. 4, April (2002) 
    9. G. Gildenblat, T. L. Chen and P. Bendix, 'Analytical application for perturbation of MOSFET sufrace potential by polysilicon depletion layer,' IEE Electronic Letters, Vol.. 35, No. 22, 28th October (1999) 
    10. N. Arora and C. Huang, 'Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance,' IEEE Transactions on Electron Devices, Vol. 42, No. 5, May (1995) 
    11. F. Gamiz et al., 'Effect of polysilicon depletion charge on electron mobility in ultrathin oxide MOSFETs,' Semiconductor Science and Technology, Vol. 18, No. 11, November (2003) 
  • 이 논문을 인용한 문헌 (1)

    1. 2017. "" Journal of semiconductor technology and science, 17(5): 709~716     

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