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Journal of semiconductor technology and science v.7 no.4, 2007년, pp.241 - 246  
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Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology

Kim, Kyung-Ki   (Department of Electrical and Computer Engineering, Northeastern University  ); Kim, Yong-Bin   (Department of Electrical and Computer Engineering, Northeastern University  ); Lee, Young-Jun   (NextChip Corp  );
  • 초록

    This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.


  • 주제어

    Phase-Locked Loop (PLL) .   Power Supply Noise .   Leakage Current.  

  • 참고문헌 (8)

    1. Xiaolue Lai, and et al., 'Fast, accurate prediction of PLL jitter induced by power grid noise', IEEE CICC 2004, pp. 121-124,2004 
    2. Reuven Holzer, 'A 1V CMOS PLL Designed in High-Leakage CMOS process Operating at 10700MHz', IEEE International Solid State Circuits Conference, Vol. 2, pp. 220-482, Feb. 2002 
    3. Koichiro Ishibashi, Tetsuya Fujimoto, and et al., 'Low-Voltage and Low-Power Logic, memory, and Analog Circuit Techniques for SoCs Using 90 nm Technologyand Beyond',IEICE Trans. Electron., Vol. E89-C, No.3, Mar. 2006 
    4. She Lin, and Norman Chang, 'Challenges in PowerGround Integrity', IEEE ICCAD 2001, pp. 651-654,2001 
    5. Payam Heydari, and Massoud Pedram, 'JitterInduced Power/Ground Noise in CMOS PLLs: A Design Perspective', Proceedings ofthe international Conference on Computer Design: VLSI in Computers & Processors (ICCD'01), pp. 209-213, 2001 
    6. Anne-Johan Annema, Bram Nauta, et al., 'Analog Circuits in Ultra-Deep-Submicron CMOS', IEEE Journal ofSolid-State Circuits, Vol. 40, No.1, Jan. 2005 
    7. Anantha Chandrakasan, William J. Bowhill, and Frank Fox, 'Design of High-Performance Microprocessor Circuits', IEEE Press, 2000 
    8. Shouli Yan, and Edgar Sanchez-Sinencio, 'Low Voltage Analog Circuit Design Techniques: A Tutorial', IEICE Trans. Analog Integrated Circuits and Systems, vol. E00-A, No.2, Feb. 2000 

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