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Journal of semiconductor technology and science v.9 no.4, 2009년, pp.192 - 197   피인용횟수: 1

A 2.4 /5.2-GHz Dual Band CMOS VCO using Balanced Frequency Doubler with Gate Bias Matching Network

Choi, Sung-Sun    (Dep. EE., Gwangju Institute of Science and Technology   ); Yu, Han-Yeol    (Dep. EE., Gwangju Institute of Science and Technology   ); Kim, Yong-Hoon    (Dep. EE., Gwangju Institute of Science and Technology  );
  • 초록

    This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.


  • 주제어

    CMOS .   dual band .   VCO .   frequency doubler .   gate bias matching network.  

  • 참고문헌 (11)

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  • 이 논문을 인용한 문헌 (1)

    1. 2011. "" Journal of semiconductor technology and science, 11(1): 59~64     

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