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Journal of semiconductor technology and science v.9 no.4, 2009년, pp.198 - 204   피인용횟수: 2

Design of a Reliable Broadband I/O Employing T-coil

Kim, Seok    (Department of Semiconductor Systems Engineering, Sungkyunkwan University   ); Kim, Shin-Ae    (Department of Semiconductor Systems Engineering, Sungkyunkwan University   ); Jung, Goeun    (Department of Semiconductor Systems Engineering, Sungkyunkwan University   ); Kwon, Kee-Won    (Department of Semiconductor Systems Engineering, Sungkyunkwan University   ); Chun, Jung-Hoon    (Department of Semiconductor Systems Engineering, Sungkyunkwan University  );
  • 초록

    Inductive peaking using T-coils has been widely used in broadband I/O interfaces. In this paper, we analyze technical effects and limitations of the T-coil, and discuss several methods that can overcome these restrictions and improve the practicality of the T-coil. In particular we also propose and verify a circuit topology which can further extend bandwidth beyond the limit that conventional T-coil can achieve, and transfer 20 Gb/s data without noticeable distortion.


  • 주제어

    Inductive peaking .   T-coil .   ESD .   high-speed interface .   reliability.  

  • 참고문헌 (10)

    1. C. Ito, K. Banerjee and R. Dutton, "Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs," IEEE Trans. Electron Devices, vol.49, No.8, pp.1444-1454, Aug., 2002 
    2. S. Galal and B. Razavi, "Broadband ES protection circuits in CMOS technology," IEEE J. Solid-State Circuits, vol.38, no.12, pp.2334-2340, Dec., 2003 
    3. S. Galal and B. Razavi, "40-Gb/s amplifier and ESD protection circuit in 0.18-um CMOS technology," IEEE J. Solid-State Circuits, vol.39, no.12, pp.2389- 2396, Dec., 2004 
    4. D. Linten and G. Groeseneken, "T-Diodes - A Novel Plug-and-PLAT Wideband RF Circuit ESD Protection Methodology," EOS/ESD symposium 2007, 242-249 
    5. T. H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits", 2nd edition: Cambridge, 2004 
    6. T. True, "Bridged-T Termination Network" U.S. Patent 3 155 927, 1964 
    7. J. Paramesh and D. J. Allstot, "Analysis of the bridged T-coil circuit using the extra-element theorem," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.53, no.12, pp.1408-1412, Dec., 2006 
    8. B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, "Distributed ESD protection for high-speed integrated circuits," IEEE Electron Device Lett., vol.21, pp.390-392, Aug., 2000 
    9. J. Chun, "ESD protection circuits for advanced CMOS technologies," Ph.D Dissertation, Stanford University, 2006 
    10. A. Amerasekera and C. Duvvury, "ESD in Silicon Integrated Circuits", 2nd edition: Wiley, 2002 
  • 이 논문을 인용한 문헌 (2)

    1. Lee, Kyoung-Su ; Jung, Go-Eun ; Kwon, Kee-Won ; Chun, Jung-Hoon 2010. "ESD Failure Analysis of PMOS Transistors" 電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, 47(2): 40~50     
    2. Kim, Seok ; Kwon, Kee-Won ; Chun, Jung-Hoon 2010. "Design of ESD Protection Circuits for High-Frequency Integrated Circuits" 電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, 47(8): 36~46     

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