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Library-based Mapping of Application to Reconfigurable Array Architecture

Han, Kyu-Seung    (Design Automation Lab, Seoul National University   ); Choi, Ki-Young    (Design Automation Lab, Seoul National University  );
  • 초록

    Reconfigurable array architecture is recently attracting much attention. It is a flexible hardware architecture, which can dynamically change its configuration to execute various functions while maintainning high performance. However, pursuing flexibility and performance at the same time leads to complexity, thereby makes the mapping of applications a difficult process. There have been attempts to use compiler or high level synthesis techniques to solve the problem. In this paper, we propose yet another method, which uses libraries for the mapping to provide an abstracttion of the internal structure and at the same time to reduce the development time and efforts through the automated process. We have selected a JPEG decoder as an example to apply the proposed method. As a result, we obtained about 20% less performance compared to manual mapping but development time is dramatically reduced to less than 1%.


  • 주제어

    Reconfigurable array .   architecture .   mapping .   parameterized library .   multimedia.  

  • 참고문헌 (8)

    1. J. Lee, K. Choi, and N.D. Dutt, "An algorithm for mapping loops onto coarse-grained reconfigurable architectures," in Proc. ACM Workshop on Languages, Compilers, Tools for Embedded Systems, pp.183-188, Jun. 2003 
    2. M. Ahn, J. W. Yoon, Y. Paek, Y. Kim, M. Kiemb, and K. Choi, "A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures," in Proc. Design, Automation and Test in Europe, pp. 363-368, Mar. 2006 
    3. T. Toi, N. Nakamura, Y. Kato, T. Awashima, K. Wakabayashi, and L. Jing, "High-level synthesis challenges and solutions for a dynamically reconfigurable processor," in Proc. ICCAD, Nov. 2006 
    4. J. Lee, K. Choi, and N.D. Dutt, "Compilation approach for coarse-grained reconfigurable architectures," IEEE Design & Test of Computers, vol. 20, pp. 26-33, Jan./Feb. 2003 
    5. B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins, "DRESC: a retargetable compiler for coarse-grained reconfigurable architectures," in Proc. ICFPT, 2002 
    6. G. Lee, S. Lee, and K. Choi, "Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques," in Proc. ISOCC, 2008 
    7. W.-H. Chen, C.H. Smith, and S.C. Fralick, "A fast computational algorithm for the discrete cosine transform," IEEE Trans. on Communications, vol. COM-25, pp. 1004?1009, Sep. 1977 
    8. M. Jo, V.K.P. Arava, H. Yang, and K. Choi, "Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture," in Proc. IEEE International SOC Conference, pp.127-130, Sep. 2007 

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