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Journal of semiconductor technology and science v.9 no.4, 2009년, pp.233 - 239   피인용횟수: 1

Mixed CT/DT Cascaded Sigma-Delta Modulator

Lee, Kye-Shin    (Department of Electronics Engineering, Sun Moon University  );
  • 초록

    A mixed CT/DT 2-1 cascaded ${\Sigma\Delta}M$ which includes a first stage CT ${\Sigma\Delta}M$ and a second stage mismatch insensitive two-channel time-interleaved DT ${\Sigma\Delta}M$ is proposed. With this approach, the advantages of both CT and DT ${\Sigma\Delta}Ms$ including high speed operation, inherent anti-aliasing filter, and good coefficient matching can be achieved. The two-channel time-interleaved ${\Sigma\Delta}M$ used in the second stage alleviates the speed constraints of the DT ${\Sigma\Delta}M$ , whereas enables better matching between the analog and digital filter coefficients compared to CT ${\Sigma\Delta}Ms$ .


  • 주제어

    Cascaded sigma-delta modulator .   continuous-time .   discrete-time .   time-interleaved .   high speed .   matching.  

  • 참고문헌 (16)

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    12. M. Maghami and M. Yavari, "Multirate doublesampling hybrid CT/DT sigma-delta modulator for wideband applications," IEEE Int. Symposium on Circuits and Systems, May 2009, pp.2253-2256 
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    14. G. Mitteregger, C. Ebner, S. Mechnig, S. Blon, T. Holuigue, and E. Romani, 'A 20mW 640MHz CMOS continuous-time $\Sigma\Delta$ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,' IEEE J. Solid State Circuits Vol.41, pp. 2641-2649, Dec., 2006 
    15. S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, New York, 1996 
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  • 이 논문을 인용한 문헌 (1)

    1. 2016. "" Journal of semiconductor technology and science, 16(3): 319~329     

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