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Transactions on electrical and electronic materials v.11 no.3, 2010년, pp.93 - 105   피인용횟수: 3
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Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics

Kim, Yong-Bin    (Department of Electrical and Computer Engineering, Northeastern University  );
  • 초록

    Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.


  • 주제어

    Nanoscale complementary metal-oxide-semiconductor .   Scaling .   Small-geometry effects .   Short channel effects .   Silicon-on-insulator technology .   Nanoelectronics.  

  • 이미지/표/수식 (14)

    • Trend of supply voltage and threshold voltage scaling.
    • Power density trends between the active power and standby leakage power with CMOS Technology scaling: supply voltage scaling is essential to decrease overall power dissipation.
    • Characteristics of sub-threshold conduction.
    • Threshold voltage roll-off and drain induced barrier lowering (DIBL).
    • Cross-section of an advanced MOSFET.
    • (a) Various leakage mechanisms in a MOSFET (left), (b) I<sub>OFF, min</sub> is the minimum achievable leakage current in a MOSFET. In low E<sub>G</sub> materials it is generally limited by I<sub>BTBT</sub>.
    • Cross-section of a SOI MOSFET.
    • Various SOI device: (a) Single gate SOI transistor, (b) double gate planar SOI transistor, (c) double gatenon-planar FinFET, (d) trigate FET, (e) quadruple-gate (or gate-all-around) FET, and gate-allaround (or surrounding gate) FET (nanowire FET).
    • MOSFET with a strained-silicon channel.
    • Schematic of a basic Single electron transistor.
    • Four dot QCA cells.
    • Fundamental QCA devices (a) binary wire, (b) QCA inverter, (c) majority logic gate.

    논문관련 이미지

  • 참고문헌 (98)

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  • 이 논문을 인용한 문헌 (3)

    1. 2013. "" Transactions on electrical and electronic materials, 14(6): 291~294     
    2. 2014. "" Transactions on electrical and electronic materials, 15(3): 149~154     
    3. 2014. "" ETRI journal, 36(1): 89~98     

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