본문 바로가기
HOME> 논문 > 논문 검색상세

논문 상세정보

대한임베디드공학회논문지 = IEMEK Journal of embedded systems and applications v.13 no.5, 2018년, pp.245 - 252  
본 등재정보는 저널의 등재정보를 참고하여 보여주는 베타서비스로 정확한 논문의 등재여부는 등재기관에 확인하시기 바랍니다.

낮은 쓰기 성능을 갖는 비휘발성 메인 메모리 시스템을 위한 성능 및 에너지 최적화 기법
Performance and Energy Optimization for Low-Write Performance Non-volatile Main Memory Systems

정우순   (Daegu University  ); 이형규   (Daegu University  );
  • 초록

    Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.


  • 주제어

    Non-Volatile RAM .   Phase-Change memory .   Cache memory .   Proactive cache.  

  • 참고문헌 (16)

    1. R. F. Freitas, W. W. Wilcke, "Storage-class memory: the Next Storage System Technology," Journal of Research and Development, Vol. 52, No. 4/5, pp. 439-447, 2008. 
    2. T. Nirschl, J.B. Philipp, T.D. Happ, C.W. Burr, B. Rajendran, M. Lee, E. Joseph, "Write Strategies for 2 and 4-bit Multi-level Phase-change Memory," Proceedings of the IEEE International Electron Device Meeting, pp. 461-464, 2007. 
    3. M.K. Qureshi, M.M. Franceschini, J.P. Karidis, "Morphable Memory System: a Roust Architecture for Exploiting Multi-level Phase Change Memories," Proceedings of International Symposium on Computer Architecture, pp. 154-162, 2010. 
    4. B. Jung, J. Lee, "High Performance PCM&DRAM Hybrid Memory System," in IEMEK Journal of Embedded Systems and Applications, Vol. 11, No. 2, pp. 117-123, 2016 (in Korean), 
    5. G. Dhiman, R. Ayoub, T. Rosing, "PDRAM: a Hybrid PRAM and DRAM Main Memory System," Proceedings of the 46th Annual Design Automation Conference, pp. 464-469, 2009, 
    6. S. Lee, H. Banh, S. Noh, "CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures," IEEE Transactions on Computers, Vol. 63, No. 9, pp. 2187-2200, 2014. 
    7. X. Cai L. Jum M. Zhao, Z. Sun, Z. Jia, "A Novel Page Caching Policy for PCM and DRAM of Hybrid Memory Architecture," 13th International Conference on Embedded Software and Systems (ICESS), pp. 67-73, 2016. 
    8. M. K. Qureshi, M. M. Franceschini, L. A. Lastras-montano, "Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing," in International Symposium On High-Performance Computer Architecture, 2010. 
    9. M. K. Qureshi, V. Slinivasan, J. A. Rivers, "Scalable High Performance Main Memory System Using Phase-change Memory Technology," in International Symposium on Computer Architecture, 2009. 
    10. S. Back, H. Lee, C. Nicopoulos, J. Kim, "Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual Phase Compression," ACM Transaction on Design Automation or Electronic Systems, Vol. 20, No. 1, 2014 
    11. S. Haoux, G.W. Burr, M.J. Breitwisch, C.T.Rettner, Y.C. CHen, R.M. Shelby, C.H. Lam, “Phase-change Random Access Memory: a Scalable Technology,” IBM Journal of Research and Development, Vol. 52, No. 4/5, pp. 465-479, 2008. 
    12. P.S. Magnsusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, B. Werner, “Simics: a Full System Simulation Platform,” Computer, Vol. 35, No. 2, pp. 50-58, 2002. 
    13. S. Kang W. Cho, B.H. Cho, K.J. Lee, C.S. Lee, H.R. Ohm Y.H. Ro, "A 0.1/ spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM," in International Solid-State Circuits Conference, pp. 487 - 496, 2006. 
    14. A. P. Ferreira, B. Childers, R. Melhem, D. Mossee, M. Yousif, "Using PCM in Next-generation Embedded Space Applications," IEEE Real-Time and Embedded Technology and Applications Symposium, 2010. 
    15. Samsung Electronics, "DDR2 registered SDRAM module, M393T5160QZA," Datasheet 저전력 시스템 
    16. C. Bienia, S.Kumar, J.P. Singh, K. Li, "The PARSEC Benchmark Suite: Characterization and Architecture Implications," Proceedings of the International Conference on Parallel Architectures and Compilation Technique, pp. 50-58, 2002. 

 저자의 다른 논문

  • Lee, Hyung Gyu (3)

    1. 2014 "Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM" Journal of semiconductor technology and science 14 (6): 741~749    
    2. 2017 "NVDIMM의 동작 특성 분석 및 개선 방안 연구" 대한임베디드공학회논문지 = IEMEK Journal of embedded systems and applications 12 (3): 177~184    
    3. 2018 "무인운반차(AGV)의 주행경로 및 위치인식을 위한 라인스캔카메라를 이용한 패턴인식 알고리즘 구현" 한국산업정보학회논문지 = Journal of the Korea Industrial Information Systems Research 23 (1): 13~21    

 활용도 분석

  • 상세보기

    amChart 영역
  • 원문보기

    amChart 영역

원문보기

무료다운로드
유료다운로드
  • 원문이 없습니다.

유료 다운로드의 경우 해당 사이트의 정책에 따라 신규 회원가입, 로그인, 유료 구매 등이 필요할 수 있습니다. 해당 사이트에서 발생하는 귀하의 모든 정보활동은 NDSL의 서비스 정책과 무관합니다.

원문복사신청을 하시면, 일부 해외 인쇄학술지의 경우 외국학술지지원센터(FRIC)에서
무료 원문복사 서비스를 제공합니다.

NDSL에서는 해당 원문을 복사서비스하고 있습니다. 위의 원문복사신청 또는 장바구니 담기를 통하여 원문복사서비스 이용이 가능합니다.

이 논문과 함께 출판된 논문 + 더보기