A 24 GHz High Frequency-Sweep Linearity FMCW Signal Generator with Floating-Shield Distributed Metal Capacitor Bank
A 24 GHz FMCW generator based on ADPLL was implemented in this work. Two-point modulation technology was used to achieve high sweep linearity. Meanwhile, a floating shield distributed metal capacitor bank was proposed to provide high frequency-sweep linearity DCO. By using these technologies, the FMCW generator’s frequency error can be controlled as small as 60 kHz rms when 180 MHz frequency was swept in 1.3 ms. High speed part of the FMCW generator was fabricated in 65 nm CMOS technology and the low speed digital part was implemented on FPGA. Power consumption of the chip excluding IO buffers is 29 mW.