논문 상세정보
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement
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초록
In this brief, we present a digital pulsewidth modulation buck converter with a switching loss reduction scheme to improve conversion efficiency at light load conditions. The proposed switching loss reduction scheme combines power-stage voltage swing scaling, transistor width scaling, and controller voltage scaling to reduce the dynamic power dissipation of the system. The power-stage voltage swing scaling also reduces the inductor current ripple at light load conditions, which extends the available output current range in the continuous conduction mode (CCM). A duty ratio estimation mechanism is implemented to provide a modulated signal with the correct duty ratio to control the output voltage. Experimental results demonstrate a 38% conversion efficiency improvement at a 50- $\mu \text{A}$ output current. In addition, the proposed circuit achieves a 96% peak efficiency with an output current ranging from 20 $\mu \text{A}$ to 30 mA in the CCM operation.
활용도 분석
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Table of contents
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
- Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template