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International journal of electrical power & energy systems v.99, 2018년, pp.650 - 658   SCIE
본 등재정보는 저널의 등재정보를 참고하여 보여주는 베타서비스로 정확한 논문의 등재여부는 등재기관에 확인하시기 바랍니다.

A new approach for FPGA-based real-time simulation of power electronic system with no simulation latency in subsystem partitioning

Liu, Chen (Corresponding author. ) ; Ma, Rui ; Bai, Hao ; Gechter, Franck ; Gao, Fei ;
  • 초록  

    Abstract In real-time Hardware-in-the-Loop (HIL) test applications for power electronic systems, the main hurdle is to tackle with the mathematical models of variable topology of complex and high frequency driven converter. The most widespread solution is to separate the whole system into subsystems. However, partitioning method usually introduces simulation time step latency between different subsystems, which causes numeric instabilities especially when stiff situation occurs. In this paper, we propose a novel parallel simulation approach which has no time step latency in the whole system division, from which a numerically stable system modeling can be realized. Its numerical accuracy of the solution, the architecture design, and the issue pertaining to the parallel calculation are discussed in detail in this paper. The pertinence of the developed solution is also tested using a case study relating to a traction system power electronic application. For this case study, implementations are made both on a 3 GHz Xeon CPU of RT LAB real-time simulator with a 2 μs simulation step and a Field Programmable Gate Arrays (FPGA) Kintex-7 embedded in National Instruments FlexRIO PXIe-7975 enabling a simulation step below 50 ns. Besides, comparison with results obtained from Simpower system in Matlab allows to evaluate the accuracy of our proposed modeling approach. Highlights We devise parallel Predictor-Corrector method to model power electronic system. A parallel subsystem division method is also proposed. We build the model of electrical traction system for transportation application. Simulation step of 2us is achieved; it’s faster than the algorithm in RT LAB. A 50 ns calculation time is also made in FPGA. Simulation results have high agreement with reference from Matlab/Simulink.


  • 주제어

    Real-time simulation .   Circuit partitioning .   Power electronic system .   Parallel calculation .   Traction system .   FPGA.  

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