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IEEE transactions on very large scale integration ... 41건

  1. [해외논문]   Table of contents  


    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. C1 - C4 , 2017 , 1063-8210 ,

    초록

    Presents the table of contents for this issue of the publication.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  2. [해외논문]   IEEE Transactions on Very Large Scale Integration (VLSI) Systems  


    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. C2 - C2 , 2017 , 1063-8210 ,

    초록

    Provides a listing of the editorial board, current staff, committee members and society officers.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  3. [해외논문]   IEEE Transactions on Very Large Scale Integration (VLSI) Systems  


    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. C3 - C3 , 2017 , 1063-8210 ,

    초록

    Provides a listing of the editorial board, current staff, committee members and society officers.

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    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  4. [해외논문]   RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing   SCIE

    Zendegani, Reza , Kamal, Mehdi , Bahadori, Milad , Afzali-Kusha, Ali , Pedram, Massoud
    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. 393 - 401 , 2017 , 1063-8210 ,

    초록

    In this paper, we propose an approximate multiplier that is high speed yet energy efficient. The approach is to round the operands to the nearest exponent of two. This way the computational intensive part of the multiplication is omitted improving speed and energy consumption at the price of a small error. The proposed approach is applicable to both signed and unsigned multiplications. We propose three hardware implementations of the approximate multiplier that includes one for the unsigned and two for the signed operations. The efficiency of the proposed multiplier is evaluated by comparing its performance with those of some approximate and accurate multipliers using different design parameters. In addition, the efficacy of the proposed approximate multiplier is studied in two image processing applications, i.e., image sharpening and smoothing.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  5. [해외논문]   Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template  

    Chong, Kwen-Siong ; Ho, Weng-Geng ; Lin, Tong ; Gwee, Bah-Hwee ; Chang, Joseph S.
    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. 402 - 415 , 2017 , 1063-8210 ,

    초록

    We propose a novel asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high operational robustness, high speed, and low power dissipation. There are five key features of our proposed SAHB. First, the SAHB cell embodies the async QDI 4-phase ( $4\phi )$ signaling protocol to accommodate process-voltage–temperature variations. Second, the sense amplifier (SA) block in SAHB cells embodies a cross-coupled latch with a positive feedback mechanism to speed up the output evaluation. Third, the evaluation block in the SAHB comprises both nMOS pull-up and pull-down networks with minimum transistor sizing to reduce the parasitic capacitance. Fourth, both the evaluation block and SA block are tightly coupled to reduce redundant internal switching nodes. Fifth, the SAHB cell is designed in CMOS static logic and hence appropriate for full-range dynamic voltage scaling operation for $\text{V}_{\mathrm {\mathbf {DD}}}$ ranging from nominal voltage (1 V) to subthreshold voltage ( $\sim 0.3$ V). When six library cells embodying our proposed SAHB are compared with those embodying the conventional async QDI precharged half-buffer (PCHB) approach, the proposed SAHB cells collectively feature simultaneous $\sim 64$ % lower power, $\sim 21$ % faster, and $\sim 6$ % smaller IC area; the PCHB cell is inappropriate for subthreshold operation. A prototype 64-bit Kogge-Stone pipeline adder based on the SAHB approach (at 65 nm CMOS) is designed. For a 1-GHz throughput and at nominal $\text{V}_{\mathrm {\mathbf {DD}}}$ , the design based on the SAHB approach simultaneously features $\sim 56$ % lower energy and $\sim 24$ % lower transistor count advantages than its PCHB counterpart. When benchmarked against the ubiquitous synchronous logic counterpart, our SAHB dissipates $\sim 39$ % lower energy at the 1-GHz throughput.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  6. [해외논문]   Variation Resilient Power Sensor With an 80-ns Response Time for Fine-Grained Power Management   SCIE

    Bhagavatula, Srikar , Jung, Byunghoo
    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. 416 - 426 , 2017 , 1063-8210 ,

    초록

    This paper presents real-time on-chip power and temperature sensors that provide fine-grained estimates for power consumption in systems-on-chip and also provide a concurrent temperature estimate for dynamic power and temperature management. This sensor occupies an area of 0.01 mm 2 in a 0.13- $\mu \text{m}$ CMOS technology. With a simplified one-point calibration and a response time of 80 ns, it shows improvements in input dynamic range by ten times, response time by six times, and sensitivity by three times over previous such sensors. A compact low-power current reference with a 3- $\sigma _{\text {max}}$ TC of 127 ppm/°C and a line regulation of 1%/V is also presented, which is used in a replica-structure-based online calibration scheme, resulting in improved tolerance to variations in process, voltage, and temperature (PVT) and degradation due to supply noise as well as aging.

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    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  7. [해외논문]   Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era   SCIE

    Rahmani, Amir M. , Haghbayan, Mohammad-Hashem , Miele, Antonio , Liljeberg, Pasi , Jantsch, Axel , Tenhunen, Hannu
    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. 427 - 440 , 2017 , 1063-8210 ,

    초록

    Power management of networked many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates considering network characteristics at runtime to achieve better performance while honoring the peak power upper bound. On the other hand, power management has a direct effect on chip temperature, which is the main driver of the aging effects. Therefore, alongside performance fulfillment, the controlling mechanism must also consider the current cores’ reliability in its actuator manipulation to enhance the overall system lifetime in the long term. In this paper, we propose a multiobjective dynamic power management technique that uses current power consumption and other network characteristics including the reliability of the cores as the feedback while utilizing fine-grained voltage and frequency scaling and per-core power gating as the actuators. In addition, disturbance rejecter and reliability balancer are designed to help the controller to better smooth power consumption in the short term and reliability in the long term, respectively. Simulations of dynamic workloads and mixed criticality application profiles show that our method not only is effective in honoring the power budget while considerably boosting the system throughput, but also increases the overall system lifetime by minimizing aging effects by means of power consumption balancing.

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    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  8. [해외논문]   Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique   SCIE

    Hashemi Namin, Shoaleh , Wu, Huapeng , Ahmadi, Majid
    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. 441 - 449 , 2017 , 1063-8210 ,

    초록

    In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major components, namely, switching power and internal power. In this paper, we present a low-power design for a digit-serial finite field multiplier in GF $(2^{m})$ . In the proposed design, a factoring technique is used to minimize switching power. To the best of our knowledge, factoring method has not been reported in the literature being used in the design of a finite field multiplier at an architectural level. Logic gate substitution is also utilized to reduce internal power. Our proposed design along $\vphantom {_{A}}$ with several existing similar works have been realized for GF $(2^{233})$ on ASIC platform, and a comparison is made between them. The synthesis results show that the proposed multiplier design consumes at least 27.8% lower total power than any previous work in comparison.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  9. [해외논문]   Scenario-Aware Dynamic Power Reduction Using Bias Addition   SCIE

    Rangachari, Sundarrajan , Balakrishnan, Jaiganesh , Chandrachoodan, Nitin
    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. 450 - 461 , 2017 , 1063-8210 ,

    초록

    Typical modern communication systems operate over a wide dynamic range of signal strengths. We consider the approach of adding a bias as offset to reduce switching activity, and study the average bit toggle for signals with different distributions, as a function of signal span and the actual bias value added. From the analysis, we provide guidelines to choose an optimal bias value, based on the system scenario, to obtain the lowest power consumption. Simulation results confirm the accuracy of the theoretical analysis. Various finite-impulse response filter architectures are evaluated, and we propose suitable enhancements to them to enable improved power savings. We apply the bias addition technique and the proposed architectural enhancements to a wireless local area network digital receiver chain, and demonstrate that over 25% power savings can be achieved under different signal conditions.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  10. [해외논문]   Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations   SCIE

    Raha, Arnab , Venkataramani, Swagath , Raghunathan, Vijay , Raghunathan, Anand
    IEEE transactions on very large scale integration (VLSI) systems v.25 no.2 ,pp. 462 - 475 , 2017 , 1063-8210 ,

    초록

    Approximate computing is an emerging design paradigm that exploits the intrinsic ability of applications to produce acceptable outputs even when their computations are executed approximately. In this paper, we explore approximate computing for a key computation pattern, reduce-and-rank (RnR), which is prevalent in a wide range of workloads, including video processing, recognition, search, and data mining. An RnR kernel performs a reduction operation (e.g., distance computation, dot product, and L1-norm) between an input vector and each of a set of reference vectors, and ranks the reduction outputs to select the top reference vectors for the current input. We propose three complementary approximation strategies for the RnR computation pattern. The first is interleaved reduction-and-ranking, wherein the vector reductions are decomposed into multiple partial reductions and interleaved with the rank computation. Leveraging this transformation, we propose the use of intermediate reduction results and ranks to identify future computations that are likely to have a low impact on the output, and can, hence, be approximated. The second strategy, input-similarity-based approximation, exploits the spatial or temporal correlation of inputs (e.g., pixels of an image or frames of a video) to identify computations that are amenable to approximation. The third strategy, reference vector reordering, rearranges the order in which the reference vectors are processed such that vectors that are relatively more critical in evaluating the correct output, are processed at the beginning of RnR operation. The number of these critical reference vectors is usually small, which renders a substantial portion of the total computation to be amenable to approximation. These strategies address a key challenge in approximate computing—identification of which computations to approximate—and may be used to drive any approximation mechanism, such as computation skipping or precision scaling to realize performance and energy improvements. A second key challenge in approximate computing is that the extent to which computations can be approximated varies significantly from application to application, and across inputs for even a single application. Hence, input-adaptive approximation, or the ability to automatically modulate the degree of approximation based on the nature of each individual input, is essential for obtaining optimal energy savings. In addition, to enable quality configurability in RnR kernels, we propose a kernel-level quality metric that correlates well to application-level quality, and identify key parameters that can be used to tune the proposed approximation strategies dynamically. We develop a runtime framework that modulates the identified parameters during the execution of RnR kernels to minimize their energy while meeting a given target quality. To evaluate the proposed concepts, we designed quality-configurable hardware implementations of six RnR-based applications from the recognition, mining, search, and video processing application domains in 45-nm technology. Our experiments demonstrate a $1.13\times $ – $3.18\times $ reduction in energy consumption with virtually no loss in output quality (<0.5%) at the application level. The energy benefits further improve up to $3.43\times $ and $3.9\times $ when the quality constraints are relaxed to 2.5% and 5%, respectively.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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