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T : 목차정보

ETRI journal 22건

  1. [국내논문]   A Low Power 16-Bit RISC Microprocessor Using ECRL Circuits  

    Shin, Young-Joon (Department of Electronic Engineering, Soongsil University ) , Lee, Chan-Ho (Department of Electronic Engineering, Soongsil University ) , Moon, Yong (Department of Electronic Engineering, Soongsil University)
    ETRI journal v.26 no.6 ,pp. 513 - 519 , 2004 , 1225-6463 ,

    초록

    This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  2. [국내논문]   An Efficient Built-in Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories  

    Kang, Dong-Chual (School of Electrical Engineering, University of Ulsan ) , Park, Sung-Min (Department of Information Electronics Engineering, Ewha Womans University ) , Cho, Sang-Bock (School of Electrical Engineering, University of Ulsan)
    ETRI journal v.26 no.6 ,pp. 520 - 534 , 2004 , 1225-6463 ,

    초록

    As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  3. [국내논문]   Error Concealment Based on Semantic Prioritization with Hardware-Based Face Tracking  

    Lee, Jae-Beom (Mamurian Design ) , Park, Ju-Hyun (Mamurian Design ) , Lee, Hyuk-Jae (School of Electrical Engineering & Computer Science, Seoul National University ) , Lee, Woo-Chan (School of Electrical Engineering & Computer Science, Seoul National University)
    ETRI journal v.26 no.6 ,pp. 535 - 544 , 2004 , 1225-6463 ,

    초록

    With video compression standards such as MPEG-4, a transmission error happens in a video-packet basis, rather than in a macroblock basis. In this context, we propose a semantic error prioritization method that determines the size of a video packet based on the importance of its contents. A video packet length is made to be short for an important area such as a facial area in order to reduce the possibility of error accumulation. To facilitate the semantic error prioritization, an efficient hardware algorithm for face tracking is proposed. The increase of hardware complexity is minimal because a motion estimation engine is efficiently re-used for face tracking. Experimental results demonstrate that the facial area is well protected with the proposed scheme.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  4. [국내논문]   An Area Optimization Method for Digital Filter Design  

    Yoon, Sang-Hun (Department of Electronic Engineering, Hanyang University ) , Chong, Jong-Wha (Department of Electronic Engineering, Hanyang University ) , Lin, Chi-Ho (Department of Computer Science, Semyung University)
    ETRI journal v.26 no.6 ,pp. 545 - 554 , 2004 , 1225-6463 ,

    초록

    In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

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    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  5. [국내논문]   Design of Dual-Mode Digital Down Converter for WCDMA and cdma2000   피인용횟수: 1

    Kim, Mi-Yeon (MagnaChip Semiconductor Ltd. ) , Lee, Seung-Jun (Information Electronics Engineering, Ewha Womans University)
    ETRI journal v.26 no.6 ,pp. 555 - 559 , 2004 , 1225-6463 ,

    초록

    We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.

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    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  6. [국내논문]   An Analog Front-End Circuit for ISO/IEC 14443-Compatible RFID Interrogators   피인용횟수: 1

    Min, Kyung-Won (School of Electrical and Electronics Engineering, Wonkwang University ) , Chai, Suk-Byung (School of Electrical and Electronics Engineering, Wonkwang University ) , Kim, Shi-Ho (School of Electrical and Electronics Engineering, Wonkwang University)
    ETRI journal v.26 no.6 ,pp. 560 - 564 , 2004 , 1225-6463 ,

    초록

    An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a $0.25{\mu}m$ double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  7. [국내논문]   An Efficient Scheme to Achieve Differential Unitary Space-Time Modulation on MIMO-OFDM Systems  

    Liu, Shou-Yin (Department of Electrical & Computer Engineering, Hanyang University ) , Chong, Jong-Wha (Department of Electrical & Computer Engineering, Hanyang University)
    ETRI journal v.26 no.6 ,pp. 565 - 574 , 2004 , 1225-6463 ,

    초록

    Differential unitary space-time modulation (DUSTM) has emerged as a promising technique to obtain spatial diversity without intractable channel estimation. This paper presents a study of the application of DUSTM on multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems with frequency-selective fading channels. From the view of a correlation analysis between subcarriers of OFDM, we obtain the maximum achievable diversity of DUSTM on MIMO-OFDM systems. Moreover, an efficient implementation strategy based on subcarrier reconstruction is proposed, which transmits all the signals of one signal matrix in one OFDM transmission and performs differential processing between two adjacent OFDM blocks. The proposed method is capable of obtaining both spatial and multipath diversity while reducing the effect of time variation of channels to a minimum. The performance improvement is confirmed by simulation results.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  8. [국내논문]   A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications  

    Park, Chang-Hyun (System LSI Division, Samsung Electronics ) , Oh, Myung-Hwan (System LSI Division, Samsung Electronics ) , Kang, Hee-Sung (System LSI Division, Samsung Electronics ) , Kang, Ho-Kyu (System LSI Division, Samsung Electronics)
    ETRI journal v.26 no.6 ,pp. 575 - 582 , 2004 , 1225-6463 ,

    초록

    Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

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  9. [국내논문]   Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application  

    Lee, Jung-Hwan (SoC Device Team, MagnaChip Semiconductor Inc. ) , Jeon, Seong-Do (SoC Device Team, MagnaChip Semiconductor Inc. ) , Chang, Sung-Keun (Department of Electronics Engineering, Chungwoon University)
    ETRI journal v.26 no.6 ,pp. 583 - 588 , 2004 , 1225-6463 ,

    초록

    In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$ . We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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  10. [국내논문]   Optimization of Packaging Design of TWEAM Module for Digital and Analog Applications  

    Choi, Kwang-Seong (Basic Research Laboratory, ETRI ) , Lee, Jong-Hyun (Basic Research Laboratory, ETRI ) , Lim, Ji-Youn (Basic Research Laboratory, ETRI ) , Kang, Young-Shik (Basic Research Laboratory, ETRI ) , Chung, Yong-Duck (Basic Research Laboratory, ETRI ) , Moon, Jong-Tae (Basic Research Laboratory, ETRI ) , Kim, Je-Ha (Basic Research Laboratory, ETRI)
    ETRI journal v.26 no.6 ,pp. 589 - 596 , 2004 , 1225-6463 ,

    초록

    Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an $S_{11}$ of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.

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    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

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