본문 바로가기
HOME> 저널/프로시딩 > 저널/프로시딩 검색상세

저널/프로시딩 상세정보

권호별목차 / 소장처보기

H : 소장처정보

T : 목차정보

Journal of semiconductor technology and science 15건

  1. [국내논문]   Editorial  

    Kyu-Myung Choi , Eui-young Chung
    Journal of semiconductor technology and science v.7 no.4 ,pp. 214 - 214 , 2007 , 1598-1657 ,

    초록

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  2. [국내논문]   Minimizing Leakage of Sequential Circuits through Flip-Flop Skewing and Technology Mapping  

    Heo, Se-Wan (Department of Electrical Engineering KAIST ) , Shin, Young-Soo (Department of Electrical Engineering KAIST)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 215 - 220 , 2007 , 1598-1657 ,

    초록

    Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  3. [국내논문]   A New Scan Chain Fault Simulation for Scan Chain Diagnosis  

    Chun, Sung-Hoon (Department of Electrical and Electronic Engineering, Yonsei University ) , Kim, Tae-Jin (Department of Electrical and Electronic Engineering, Yonsei University ) , Park, Eun-Sei (Department of Electrical and Electronic Engineering, Yonsei University ) , Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 221 - 228 , 2007 , 1598-1657 ,

    초록

    In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  4. [국내논문]   Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing  

    Wu, Chou-Pin (Dept. of Electrical Engineering, National Tsing Hua University ) , Wu, Jen-Ming (Dept. of Electrical Engineering, National Tsing Hua University)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 229 - 234 , 2007 , 1598-1657 ,

    초록

    In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  5. [국내논문]   A SSN-Reduced 5Gb/s Parallel Transmitter  

    Lee, Seon-Kyoo (Department of Electrical Engineering, Pohang University of Science and Technology ) , Kim, Young-Sang (Department of Electrical Engineering, Pohang University of Science and Technology ) , Park, Hong-June (Department of Electrical Engineering, Pohang University of Science and Technology ) , Sim, Jae-Yoon (Department of Electrical Engineering, Pohang University of Science and Technology)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 235 - 240 , 2007 , 1598-1657 ,

    초록

    A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  6. [국내논문]   Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology  

    Kim, Kyung-Ki (Department of Electrical and Computer Engineering, Northeastern University ) , Kim, Yong-Bin (Department of Electrical and Computer Engineering, Northeastern University ) , Lee, Young-Jun (NextChip Corp)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 241 - 246 , 2007 , 1598-1657 ,

    초록

    This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  7. [국내논문]   A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions  

    Ma, Yao (Graduate School of Information, Production and Systems, Waseda University ) , Song, Yang (Graduate School of Information, Production and Systems, Waseda University ) , Ikenaga, Takeshi (Graduate School of Information, Production and Systems, Waseda University ) , Goto, Satoshi (Graduate School of Information, Production and Systems, Waseda University)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 247 - 253 , 2007 , 1598-1657 ,

    초록

    In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the $8{\times}8$ integer forward and inverse DCT transform matrices, (2) divide them into four $4{\times}4$ sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of $8{\times}8$ and matrices of $4{\times}4$ forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either $4{\times}4\;or\;8{\times}8$ transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) ( $1920{\times}1080@60Hz$ ) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  8. [국내논문]   Nanochannels for Manipulation of DNA Molecule using Various Fabrication Molecule  

    Hwang, M.T. (CIRMM/Institute of Industrial Science, The University of Tokyo ) , Cho, Y.H. (CIRMM/Institute of Industrial Science, The University of Tokyo ) , Lee, S.W. (CIRMM/Institute of Industrial Science, The University of Tokyo ) , Takama, N. (CIRMM/Institute of Industrial Science, The University of Tokyo ) , Fujii, T. (CIRMM/Institute of Industrial Science, The University of Tokyo ) , Kim, B.J. (CIRMM/Institute of Industrial Science, The University of Tokyo)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 254 - 259 , 2007 , 1598-1657 ,

    초록

    In this report, several fabrication techniques for the formation of various nanochannels (with $SiO_2$ , Si, or Quartz) are introduced. Moreover, simple fabrication technique for generating $SiO_2$ nanochannels without nanolithography is presented. By using different nanochannels, the degree of stretching DNA molecule will be evaluated. Finally, we introduce a nanometer scale fluidic channel with electrodes on the sidewall of it, to detect and analyze single DNA molecule. The cross sectional shape of the nanotrench is V-groove, which was implemented by thermal oxidation. Electrodes were deposited through both sidewalls of nanotrench and the sealing of channel was done by covering thin poly-dimethiysiloxane (PDMS) polymer sheet.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  9. [국내논문]   Signal Transient and Crosstalk Model of Capacitively and Inductively Coupled VLSI Interconnect Lines   피인용횟수: 1

    Kim, Tae-Hoon (Department of Electrical and Computer Engineering, Hanyang University ) , Kim, Dong-Chul (Department of Electrical and Computer Engineering, Hanyang University ) , Eo, Yung-Seon (Department of Electrical and Computer Engineering, Hanyang University)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 260 - 266 , 2007 , 1598-1657 ,

    초록

    Analytical compact form models for the signal transients and crosstalk noise of inductive-effect-prominent multi-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the equivalent transmission line model and transmission line parameters for fundamental modes. The signal transients and crosstalk noise expressions of two coupled lines are derived by using a waveform approximation technique. It is shown that the models have excellent agreement with SPICE simulation.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지
  10. [국내논문]   A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18-μm CMOS   피인용횟수: 4

    Shin, Jae-Wook (High-Speed Integrated Circuits and Systems Lab., Kwangwoon University ) , Kim, Jong-Sik (High-Speed Integrated Circuits and Systems Lab., Kwangwoon University ) , Kim, Seung-Soo (High-Speed Integrated Circuits and Systems Lab., Kwangwoon University ) , Shin, Hyun-Chol (High-Speed Integrated Circuits and Systems Lab., Kwangwoon University)
    Journal of semiconductor technology and science v.7 no.4 ,pp. 267 - 273 , 2007 , 1598-1657 ,

    초록

    A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

    원문보기

    원문보기
    무료다운로드 유료다운로드

    회원님의 원문열람 권한에 따라 열람이 불가능 할 수 있으며 권한이 없는 경우 해당 사이트의 정책에 따라 회원가입 및 유료구매가 필요할 수 있습니다.이동하는 사이트에서의 모든 정보이용은 NDSL과 무관합니다.

    NDSL에서는 해당 원문을 복사서비스하고 있습니다. 아래의 원문복사신청 또는 장바구니담기를 통하여 원문복사서비스 이용이 가능합니다.

    이미지

    Fig. 1 이미지

논문관련 이미지